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ARM Architecture Reference Manual- P8

ARM Architecture Reference Manual- P8: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | ARM Instructions 4.1.56 UMULL 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 876543 0 cond 0 0 0 0 1 0 0 S RdHi RdLo Rs 10 0 1 Rm The UMULL Unsigned Multiply Long instruction multiplies the unsigned value of register Rm with the unsigned value of register Rs to produce a 64-bit result. The upper 32 bits of the result are stored in RdHi . The lower 32 bits are stored in RdLo . The condition code flags are optionally updated based on the 64-bit result. Syntax UMULL cond S RdLo RdHi Rm Rs where cond Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-5. If cond is omitted the AL always condition is used. S Causes the S bit bit 20 in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiplication. If S is omitted the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. RdLo Stores the lower 32 bits of the result. RdHi Stores the upper 32 bits of the result. Rm Holds the signed value to be multiplied with the value of Rs . Rs Holds the signed value to be multiplied with the value of Rm . Architecture version All M variants Exceptions None ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A4-111 ARM Instructions Operation if ConditionPassed cond then RdHi Rm Rs 63 32 Unsigned multiplication RdLo Rm Rs 31 0 if S 1 then N Flag Z Flag C Flag V Flag RdHi 31 if RdHi 0 and RdLo 0 then 1 else 0 unaffected See C and V flags note unaffected See C and V flags note Usage UMULL multiplies unsigned variables to produce a 64-bit result in two general-purpose registers. Notes Use of R15 Specifying R15 for register RdHi RdLo Rm or Rs has UNPREDICTABLE results. Operand restriction RdHi RdLo and Rm must be three distinct registers or the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination it must be implemented on the value .