tailieunhanh - ARM Architecture Reference Manual- P4

ARM Architecture Reference Manual- P4: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | The ARM Instruction Set Coprocessor instructions The ARM instruction set provides three types of instruction for communicating with coprocessors. These allow the ARM processor to initiate a coprocessor data processing operation ARM registers to be transferred to and from coprocessor registers the ARM processor to generate addresses for the coprocessor Load and Store instructions. The instruction set distinguishes up to 16 coprocessors with a 4-bit field in each coprocessor instruction so each coprocessor is assigned a particular number. ------Note ----------------- One coprocessor can use more than one of the 16 numbers if a large coprocessor instruction set is required. Coprocessors execute the same instruction stream as ARM ignoring ARM instructions and coprocessor instructions for other coprocessors. Coprocessor instructions that cannot be executed by coprocessor hardware cause an undefined instruction trap allowing software emulation of coprocessor hardware. A coprocessor can partially execute an instruction and then cause an exception. This is useful for handling run-time-generated exceptions like divide-by-zero or overflow. However the partial execution is internal to the coprocessor and is not visible to the ARM processor. As far as the ARM processor is concerned the instruction is held at the start of its execution and completes without exception if allowed to begin execution. Any decision on whether to execute the instruction or cause an exception is taken within the coprocessor before the ARM processor is allowed to start executing the instruction. Not all fields in coprocessor instructions are used by the ARM processor. Coprocessor register specifiers and opcodes are defined by individual coprocessors. Therefore only generic instruction mnemonics are provided for coprocessor instructions. Assembler macros can be used to transform custom coprocessor mnemonics into these generic mnemonics or to regenerate the opcodes manually. Examples CDP p5 2