tailieunhanh - ARM Architecture Reference Manual- P7

ARM Architecture Reference Manual- P7: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | ARM Instructions Operation if ConditionPassed cond then RdHi Rm Rs 63 32 Signed multiplication RdLo Rm Rs 31 0 if S 1 then N Flag Z Flag C Flag V Flag RdHi 31 if RdHi 0 and RdLo 0 then 1 else 0 unaffected See C and V flags note unaffected See C and V flags note Usage SMULL multiplies signed variables to produce a 64-bit result in two general-purpose registers. Notes Use of R15 Specifying R15 for register RdHi RdLo Rm or Rs has UNPREDICTABLE results. Operand restriction RdHi RdLo and Rm must be three distinct registers or the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination it must be implemented on the value of the Rs operand. The type of early termination used signed or unsigned is IMPLEMENTATION DEFINED. C and V flags The SMULLS instruction is defined to leave the C and V flags unchanged in ARM architecture version 5 and above. In earlier versions of the architecture the values of the C and V flags were UNPREDICTABLE after an SMULLS instruction. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A4-81 ARM Instructions STC 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W 0 Rn CRd cp_num 8_bit_word_offset The STC Store Coprocessor instruction stores data from the coprocessor whose name is cp_num to the sequence of consecutive memory addresses calculated by addressing_mode . If no coprocessors indicate that they can execute the instruction an Undefined Instruction exception is generated. Syntax STC cond L coproc CRd addressing_mode STC2 L coproc CRd addressing_mode where cond Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-5. If cond is omitted the AL always condition is used. STC2 Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. L Sets the N bit bit .