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ARM Architecture Reference Manual- P5

ARM Architecture Reference Manual- P5: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | ARM Instructions Operation if ConditionPassed cond then Coprocessor cp_num -dependent operation Usage CDP is used to initiate coprocessor instructions that do not operate on values in ARM registers or in main memory. An example is a floating-point multiply instruction for a floating-point coprocessor. Notes Coprocessor fields Only instruction bits 31 24 bits 11 8 and bit 4 are architecturally defined. The remaining fields are recommendations for compatibility with ARM Development Systems. Unimplemented coprocessor instructions Hardware coprocessor support is optional regardless of the architecture version. An implementation can choose to implement a subset of the coprocessor instructions or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an undefined instruction trap. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. A4-21 ARM Instructions 4.1.12 CLZ 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 876543 0 cond 0 0 0 1 0 1 1 0 SBO Rd SBO 0 0 0 1 Rm The CLZ Count Leading Zeros instruction returns the number of binary zero bits before the first binary one bit in a register value. The source register is scanned from the most significant bit bit 31 towards the least significant bit bit 0 . The result value is 32 if no bits are set in the source register and zero if bit 31 is set. This instruction does not update the condition code flags. Syntax CLZ cond Rd Rm where cond Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-5. If cond is omitted the AL always condition is used. Rd Specifies the destination register for the operation. If R15 is specified for Rd the result is UNPREDICTABLE. Rm Specifies the source register for this operation. If R15 is specified for Rm the result is UNPREDICTABLE. Architecture version Version 5 and above Exceptions None Operation if Rm 0 Rd 32 else Rd 31 - bit position of most significant 1 in Rm Usage To