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Bài giảng Computer Architecture: Chapter 5 - Prof. Jerry Breecher

| Computer Architecture Chapter 5 - Supplement Accessing A Cache Prof. Jerry Breecher CSCI 240 Fall 2003 Chap. 5 - Supplement Overview Here we do several things. “The big picture”. How do disk, memory, cache, and processor all play together? What happens to the cache on various memory requests? Chap. 5 - Supplement What Actions Occur On A Read Reg- isters L1 Cache L2 Cache Mem Disk LD R1, (mem) Mem = address(123456) Chap. 5 - Supplement The Memory Addresses We’ll Be Asking For Here’s a number of addresses. We’ll be asking for the data at these addresses and see what happens to the cache when we do so. 1090 00000000000000000000010 0010 00010 0 4 5 8 9 31 Address Tag Set Off-set Result Miss 1440 00000000000000000000010 1101 00000 0 4 5 8 9 31 Miss 5000 xxxxxxxxxxxxxxxxxxxxxxx xxxx 01000 0 4 5 8 9 31 1470 xxxxxxxxxxxxxxxxxxxxxxx xxxx 0 4 5 8 9 31 xxxxx Chap. 5 - Supplement Here’s the Cache We’ll Be Touching Initially the cache is empty. Set Address V Tag Data (Can hold a . | Computer Architecture Chapter 5 - Supplement Accessing A Cache Prof. Jerry Breecher CSCI 240 Fall 2003 Chap. 5 - Supplement Overview Here we do several things. “The big picture”. How do disk, memory, cache, and processor all play together? What happens to the cache on various memory requests? Chap. 5 - Supplement What Actions Occur On A Read Reg- isters L1 Cache L2 Cache Mem Disk LD R1, (mem) Mem = address(123456) Chap. 5 - Supplement The Memory Addresses We’ll Be Asking For Here’s a number of addresses. We’ll be asking for the data at these addresses and see what happens to the cache when we do so. 1090 00000000000000000000010 0010 00010 0 4 5 8 9 31 Address Tag Set Off-set Result Miss 1440 00000000000000000000010 1101 00000 0 4 5 8 9 31 Miss 5000 xxxxxxxxxxxxxxxxxxxxxxx xxxx 01000 0 4 5 8 9 31 1470 xxxxxxxxxxxxxxxxxxxxxxx xxxx 0 4 5 8 9 31 xxxxx Chap. 5 - Supplement Here’s the Cache We’ll Be Touching Initially the cache is empty. Set Address V Tag Data (Can hold a 32-byte cache line.) 0 (0000) N 1 (0001) N 2 (0010) N 3 (0011) N 4 (0100) N 5 (0101) N 6 (0110) N 7 (0111) N 8 (1000) N 9 (1001) N 10 (1010) N 11 (1011) N 12 (1100) N 13 (1101) N 14 (1110) N 15 (1111) N Cache: Is Direct Mapped Contains 512 bytes. Has 16 sets. Each set can hold 32 bytes – 1 cache line. Chap. 5 - Supplement Doing Some Cache Action We want to READ data from address 1090 = 010|0010|00010 Set Address V Tag Data (Always holds a 32-byte cache line.) 0 (0000) N 1 (0001) N 2 (0010) N 3 (0011) N 4 (0100) N 5 (0101) N 6 (0110) N 7 (0111) N 8 (1000) N 9 (1001) N 10 (1010) N 11 (1011) N 12 (1100) N 13 (1101) N 14 (1110) N 15 (1111) N Add. Tag Set Offset 256 0000 1000 00000 512 0001 0000 00000 1024 0010 0000 00000 1090 0010 0010 00010 1099 0010 0010 01011 1440 0010 1101 00000 1470 0010 1101 11110 1600 0011 0010 00000 1620 0011 0010 10100 2048 0100 0000 00000 4096 1000 0000 00000 5000 1001 1100 01000 Y 00000 .10 Data from memory loc. 1088 - 1119 Chap. 5 - Supplement Doing Some