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Queueing mạng lưới và chuỗi Markov P13

This chapter considers several large applications. The set of applications organized into three sections. In Section 13.1, we present case studies queueing network applications. In Section 13.2 we present case studies Markov chains and stochastic Petri nets. In Section 13.3, case studies hierarchical models are presented. | Queueing Networks and Markov Chains Gunter Botch Stefan Greiner Hermann de Meer Kishor S. Trivedi Copyright 1998 John Wiley Sons Inc. Print ISBN 0-471-19366-6 Online ISBN 0-471-20058-1 13 Applications This chapter considers several large applications. The set of applications is organized into three sections. In Section 13.1 we present case studies of queueing network applications. In Section 13.2 we present case studies of Markov chains and stochastic Petri nets. In Section 13.3 case studies of hierarchical models are presented. 13.1 CASE STUDIES OF QUEUEING NETWORKS Five different case studies are presented in this section. These range from multiprocessor system model several networking applications one operating system model and a flexible production system model. 13.1.1 Multiprocessor Systems Models of tightly coupled multiprocessor systems will be discussed first followed by models of loosely coupled systems. 13.1.1.1 Tightly Coupled Systems Consider a tightly coupled multiprocessor system with caches at each processor and a common memory connected to the processors via a common bus see Fig. 13.1 . The system consists of m processors and a common memory with n memory modules. A processor sends a request via the common bus to one of the n memory modules when a cache miss occurs whereupon the requested data is loaded into the cache via 603 604 APPLICATIONS Pn Processor n n 1 . 5 Cn Cache n n 1 . 5 MMn Memory Module n n 1 . 4 Fig. 13.1 A multiprocessor system with caches common memory and common bus. the common bus. Figure 13.2 shows a product-form queueing network model of such a multiprocessor system. Replies to Memory Requests Replies to Memory Requests Memory Modules Fig. 13.2 Queueing network model of the multiprocessor system shown in Fig. 13.1. The m processors are modeled by an IS node and the bus and the memory modules by single server nodes. The number of requests in the system is m since a processor is either working or waiting until a memory request is