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Handbook of algorithms for physical design automation part 79

Handbook of Algorithms for Physical Design Automation part 79 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 762 Handbook of Algorithms for Physical Design Automation As mentioned in Section 36.2 CMP-induced metal dishing increases the line resistance. In addition metal height can vary as a function of line width local and global densities. It is critical to ensure the basic computational accuracy of RC extraction tools before including process variation effects. Silicon validation of parasitics helps in closing the loop between process realities and interconnect extraction 44 . 36.6.2 Impact of Spatial Variation As device and interconnect dimensions continue to shrink maintaining process uniformity is increasing in importance and difficulty 61 . The 2004 edition of the International Technology Roadmap for Semiconductors ITRS 25 lists the control of printed transistor gate length in the lithography process as falling short of expectations for the coming technology generations. Variability is happening at multiple scales in semiconductor manufacturing processes but only the largest of these scales has been studied. Statistical metrology methods are now used to model the variation of different parameters not only across the wafer but also within the die itself. The modeling of both waferlevel and die-level spatial dependencies will become increasingly important for effective process control. The quality of planarization with CMP depends on the layout feature density uniformity. In addition the features on each die follow a systematic within-die variation. Therefore different devices within the wafer will exhibit similar characteristics even though they have different characteristics within the die 3 . This interaction between wafer and die variation if not considered leads to erroneous modeling as shown in Figure 36.23. Figure 36.23a displays a one-dimensional cross section through the wafer displaying the ILD thickness over a particular device. Although the die mean or wafer-level trend across the wafer shows a small curvature the enclosing curvature of wafer and die .