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Handbook of algorithms for physical design automation part 2

Handbook of Algorithms for Physical Design Automation part 2 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | x Contents Chapter 32 Optimization Techniques in Routing.627 Christoph Albrecht Chapter 33 Global Interconnect Planning.645 Cheng-Kok Koh Evangeline F.Y. Young and Yao-Wen Chang Chapter 34 Coupling Noise.673 Rajendran Panda Vladimir Zolotov and Murat Becer PART VII Manufacturability and Detailed Routing Chapter 35 Modeling and Computational Lithography.695 Franklin M. Schellenberg Chapter 36 CMP Fill Synthesis A Survey of Recent Studies.737 Andrew B. Kahng and Kambiz Samadi Chapter 37 Yield Analysis and Optimization.771 Puneet Gupta and Evanthia Papadopoulou Chapter 38 Manufacturability-Aware Routing.791 Minsik Cho Joydeep Mitra and David Z. Pan PART VIII Physical Synthesis Chapter 39 Placement-Driven Synthesis Design Closure Tool.813 Charles J. Alpert Nathaniel Hieter Arjen Mets Ruchir Puri Lakshmi Reddy Haoxing Ren and Louise Trevillyan Chapter 40 X Architecture Place and Route Physical Design for the X Interconnect Architecture.835 Steve Teig Asmus Hetzel Joseph Ganley Jon Frankle and Aki Fujimura PART IX Designing Large Global Nets Chapter 41 Inductance Effects in Global Nets.865 Yehea I. Ismail Contents xi Chapter 42 Clock Network Design Basics.881 Chris Chu and Min Pan Chapter 43 Practical Issues in Clock Network Design.897 Chris Chu and Min Pan Chapter 44 Power Grid Design.913 Haihua Su and Sani Nassif PART X Physical Design for Specialized Technologies Chapter 45 Field-Programmable Gate Array Architectures.941 Steven J.E. Wilton Nathalie Chan King Choy Scott Y.L. Chin and Kara K. W Poon Chapter 46 FPGA Technology Mapping Placement and Routing.957 Kia Bazargan Chapter 47 Physical Design for Three-Dimensional Circuits.985 Kia Bazargan and Sachin S. Sapatnekar .