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Model-Based Design for Embedded Systems- P66

Model-Based Design for Embedded Systems- P66: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 636 Model-Based Design for Embedded Systems Static power mW vs. interconnect length optical link Dynamic power W vs. interconnect length optical link 1.4E-02 BPT 32 Si - 1.1pm pitch 0.0E 00 2.5 5 7.5 10 12.5 15 17.5 20 b Link length mm FIGURE 19.13 Power vs. interconnect length for BPT 65 45 and 32 nm technologies a Average static power in mW . b Average dynamic power in W . and to lower detector capacitance which lowers the receiver circuit quiescent current. Dynamic power reductions between Si and S2 of the order of 2-4 are observed. This is attributed mainly to lower transistor capacitances because of lower bias current in the driver due to the reduction in source threshold current and because of lower modulation currents in the driver due to the increase in source efficiency and detector responsivity . Platform for Model-Based Design of Integrated Multi-Technology Systems 637 FIGURE 19.14 a Total power in mW vs. interconnect length for BPT 65 45 and 32 nm technologies. b Average total power comparison for varying interconnect length and technologies at 1.1 gm pitch reduction factor. Using static and dynamic power information the total energy can be calculated Figure 19.14 . The overall power is shown to be reduced between S1 and S2 by factors of between 2 and 4. The greatest reduction is achieved at higher link lengths which is the expected context for the use of such optical links. For 638 Model-Based Design for Embedded Systems S2 power reduction can be considered to be a major argument in favor of optical interconnect. For Si it is clear that the static power comparison is the weak point for optical interconnect because of continuous biasing of the source avoiding turn-on times to achieve the required bit rate and of the receiver circuit the circuit bandwidth is directly related to quiescent bias current . The reduction in source threshold current and in detector capacitance in S2 has a significant impact on both these factors to the extent that the static .