Đang chuẩn bị liên kết để tải về tài liệu:
Model-Based Design for Embedded Systems- P40

Model-Based Design for Embedded Systems- P40: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 356 Model-Based Design for Embedded Systems FXINA FXINB G Inputs BY F Inputs BX CE CLK SR FX Y YQ F5 X XQ FIGURE 12.2 Simplified architecture of Xilinx Virtex 4 slice 27 . The multiplexers in the middle are primarily used to implement wide multiplexers from several slices. From Xilinx Virtex-4 FPGA User Guide ug070 v2.40 edition April 2008. With permission. where some configuration frames are reconfigured while other portions remain active. In Virtex 4 FPGAs the configuration frames themselves are organized in columns along the North-South axis of the FPGA. Each configuration frame is the height of 16 CLBs or 4 BRAM memory elements and matches the height of the clock distribution tree. Hence PR of large portions of the FPGA is best done using rectangular regions that are a multiple of 16 CLBs in that direction. In the East-West direction the columns are narrow requiring many configuration frames to configure all of the LUTs in one CLB which enables the exact size of a reconfigurable region to be more finely controlled. Note that in Virtex 2 and Virtex 2 Pro FPGAs the configuration frames cross the entire device in the North-South direction making connectivity between regions more difficult. Although PR is possible in these families rather complex architectures tend to be used 11 . FPGA Platforms for Embedded Systems 357 FIGURE 12.3 Early FPGA configuration logic 5 . phil phi2 and hold signals control loading of data into the shift chain. Blocks marked pass device are controlled by the configuration logic. From Xilinx Virtex-4 FPGA User Guide ug070 v2.40 edition April 2008. With permission. Although the logic in a design can often be floorplanned to fit the natural layout of the configuration frames signal routing is often much more problematic. For instance the FPGA architecture may require certain external I O pins to be used for certain purposes such as clock inputs. It may also be difficult to floorplan a region containing exactly the right number of external .