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Model-Based Design for Embedded Systems- P38

Model-Based Design for Embedded Systems- P38: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 336 Model-Based Design for Embedded Systems MontiumC. The Montium design methodology to map DSP applications on the Montium TP is divided into three steps 1. The high-level description of the DSP application is analyzed and computationally intensive DSP kernels are identified. 2. The identified DSP kernels or parts of the DSP kernels are mapped on one or multiple Montium TPs that are available in a SoC. The DSP operations are programmed on the Montium TP using MontiumC. 3. Depending on the layout of the SoC in which the Montium processing tiles are applied the Montium processing tiles are configured for a particular DSP kernel or part of the DSP kernel. Furthermore the channels in the NoC between the processing tiles are configured. 11.3.1.3 Annabelle Heterogeneous System-on-Chip In this section the prototype Annabelle SoC is described according to the heterogeneous SoC template mentioned before which is intended to be used for digital radio broadcasting receivers e.g. digital audio broadcasting digital radio mondiale . Figure 11.6 shows the overall architecture of the Annabelle SoC. The Annabelle SoC consists of an ARM926 GPP with a five-layer AMBA AHB four Montium TPs an NoC a Viterbi decoder two ADCs two DDCs a DMA controller SRAM SDRAM memory interfaces and external bus interfaces. The four Montium TPs and the NoC are arranged in a reconfigurable subsystem labelled reconfigurable fabric. The reconfigurable fabric is connected to the AHB bus and serves as a slave to the AMBA system. A configurable clock controller generates the clocks for the individual Montium TPs. Every individual Montium TP has its own adjustable clock and runs at its own speed. A prototype chip of the Annabelle SoC has been produced using the Atmel 130 nm CMOS process 8 . The reconfigurable fabric that is integrated in the Annabelle SoC is shown in detail in Figure 11.7. The reconfigurable fabric acts as a FIGURE 11.6 Block diagram of the Annabelle SoC. Reconfigurable MultiCore Architectures