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Sequential Verulog Topics part 1

Types of Delay Models There are three types of delay models used in Verilog: distributed, lumped, and pin-to-pin (path) delays. 10.1.1 Distributed Delay Distributed | Team LiB 10.1 Types of Delay Models There are three types of delay models used in Verilog distributed lumped and pin-to-pin path delays. 10.1.1 Distributed Delay Distributed delays are specified on a per element basis. Delay values are assigned to individual elements in the circuit. An example of distributed delays in module M is shown in Figure 10-1. Figure 10-1. Distributed Delay Distributed delays can be modeled by assigning delay values to individual gates or by using delay values in individual assign statements. When inputs of any gate change the output of the gate changes after the delay value specified. Example 101 shows how distributed delays are specified in gates and dataflow description. Example 10-1 Distributed Delays Distributed delays in gate-level modules module M out a b c d output out input a b c d wire e f Delay is distributed to each gate. and 5 a1 e a b and 7 a2 f c d and 4 a3 out e f endmodule Distributed delays in data flow definition of a module module M out a b c d output out input a b c d wire e f Distributed delay in each expression assign 5 e a b assign 7 f c d assign 4 out e f endmodule Distributed delays provide detailed delay modeling. Delays in each element of the circuit are specified. 10.1.2 Lumped Delay Lumped delays are specified on a per module basis. They can be specified as a single delay on the output gate of the module. The cumulative delay of all paths is lumped at one location. The example of a lumped delay is shown in Figure 10-2 and Example 10-2. Figure 10-2. Lumped Delay The above example is a modification of Figure 10-1. In this example we computed the maximum delay from any input to the output of Figure 10-1 which is 7 4 11 units. The entire delay is lumped into the output gate. After a delay primary output changes after any input to the module M changes. Example 10-2 Lumped Delay Lumped Delay Model module M out a b c d output out input a b c d wire e f and a1 e a b and a2 f c d and 11 a3 out e f delay only on the .