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Standard Sequential Components Tutorial part 2

Appendix C − MAX+plus II Tutorial 2 Page 1 of 11 Contents Contents | Appendix C - MAX plus II Tutorial 2 Page 1 of 11 Contents Contents.1 Appendix C MAX plus II Tutorial 2.2 C. 1 Getting Started.2 C.1.1 Preparing a Folder for the Project.2 C.1.2 Creating a Project.2 C.1.3 Editing the VHDL Source Code.2 C.2 Synthesis for Programming the PLD.3 C.3 Circuit Simulation.3 C.4 Using the Floorplan Editor.5 C.4.1 Selecting the Target Device.5 C.4.2 Maping the I O Pins with the Floorplan Editor.6 C.5 Fitting the Netlist and Pins to the PLD.7 C.6 Programming the FPGA.8 C.6.1 Connecting and Configuring the UP2 Board.8 C.6.2 Configure the ByteBlaster Cable.9 C.6.3 Selecting the File to Program.10 C.6.4 Programming the PLD.11 C.7 Testing the Hardware.11 Microprocessor Design Principles and Practices with VHDL Last updated 11 19 2003 9 10 AM Appendix C - MAX plus II Tutorial 2 Page 2 of 11 Appendix C MAX plus II Tutorial 2 In tutorial 1 we saw how a VHDL description of a 4-bit counter circuit is synthesized and simulated in MAX plus II. Test values for the input signals Clock and Reset were manually setup in the simulator. In order for the synthesized circuit to operate in hardware these input signals must be provided for by the hardware. For example the Reset signal must be connected to an input switch and a clock generator is needed for the Clock signal. Furthermore the counter output signal Q must be connected to LEDs in order for us to see that the counter is really working. In this tutorial we will expand on the counter circuit by adding a clock generator and a 7-segment decoder. The UP2 development board already has a built in clock source running at a frequency of approximately 25MHz. The clock generator circuit simply divides this clock speed down to 1Hz. The 7-segment decoder converts the 4-bit counter output to drive a 7-segment LED display. An enclosing entity top is used to connect these three entities clockdiv counter and decoder together to form one complete circuit. This circuit is then downloaded to the PLD on the UP2 development .