tailieunhanh - Bài giảng Computer Organization and Architecture: Chapter 14

Instruction Level Parallelism and Superscalar Processors thuộc Chapter 14 của "Bài giảng Computer Organization and Architecture" với các vấn đề cơ bản cần tìm hiểu về What is Superscalar; Why Superscalar; General Superscalar Organization; Superpipelined;. | William Stallings Computer Organization and Architecture 6th Edition Chapter 14 Instruction Level Parallelism and Superscalar Processors What is Superscalar? Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently Equally applicable to RISC & CISC In practice usually RISC Why Superscalar? Most operations are on scalar quantities (see RISC notes) Improve these operations to get an overall improvement General Superscalar Organization Superpipelined Many pipeline stages need less than half a clock cycle Double internal clock speed gets two tasks per external clock cycle Superscalar allows parallel fetch execute Superscalar v Superpipeline Limitations Instruction level parallelism Compiler based optimisation Hardware techniques Limited by True data dependency Procedural dependency Resource conflicts Output dependency Antidependency True Data Dependency ADD r1, r2 (r1 := r1+r2;) MOVE r3,r1 (r3 := r1;) Can . | William Stallings Computer Organization and Architecture 6th Edition Chapter 14 Instruction Level Parallelism and Superscalar Processors What is Superscalar? Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently Equally applicable to RISC & CISC In practice usually RISC Why Superscalar? Most operations are on scalar quantities (see RISC notes) Improve these operations to get an overall improvement General Superscalar Organization Superpipelined Many pipeline stages need less than half a clock cycle Double internal clock speed gets two tasks per external clock cycle Superscalar allows parallel fetch execute Superscalar v Superpipeline Limitations Instruction level parallelism Compiler based optimisation Hardware techniques Limited by True data dependency Procedural dependency Resource conflicts Output dependency Antidependency True Data Dependency ADD r1, r2 (r1 := r1+r2;) MOVE r3,r1 (r3 := r1;) Can fetch and decode second instruction in parallel with first Can NOT execute second instruction until first is finished Procedural Dependency Can not execute instructions after a branch in parallel with instructions before a branch Also, if instruction length is not fixed, instructions have to be decoded to find out how many fetches are needed This prevents simultaneous fetches Resource Conflict Two or more instructions requiring access to the same resource at the same time . two arithmetic instructions Can duplicate resources . have two arithmetic units Effect of Dependencies Design Issues Instruction level parallelism Instructions in a sequence are independent Execution can be overlapped Governed by data and procedural dependency Machine Parallelism Ability to take advantage of instruction level parallelism Governed by number of parallel pipelines Instruction Issue Policy Order in which instructions are fetched Order in which instructions are executed Order in

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• Bài giảng Computer Organization and Architecture
• Computer Organization and Architecture
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• General Superscalar Organization