tailieunhanh - ECE 551 Digital Design And Synthesis: Lecture 11

ECE 551 Digital Design And Synthesis: Lecture 11 has many contents: Standard Cell, FPGA, Custom Logic, Programming an FPGA, Configurable Routing Elements, Logic Elements, FPGA Logic Structure, Standard Cell Layouts, Standard Cells, Custom Logic, Hardware Implementations, Tech Mapping: FPGAs, Detailed Routing: FPGAs,. | ECE 551 Digital Design And Synthesis Fall ‘09 Digital Circuit Implementations: Standard Cell FPGA Custom Logic Administrative Matters HW6 Meeting (due today by 4:00PM) Now What? After synthesis, implement as hardware FPGAs Standard cells Custom logic Choose implementation based on cost and performance requirements FPGAs Field Programmable Gate Array Temporary (SRAM based) Permanent (Flash) not as common Pros Allow for very complex implementations Generally reuseable (upgrades/bugfixes/prototype) Low non-recurring engineering costs (NREs) Cons Expensive per-unit (10s-100s of $) Slower than gates Need support cirucuits (configuration loading) Not as robust (mission critical operations) Programming an FPGA Most designs based on SRAM Writing to the SRAM “configures” device Different circuits implemented based on values DATA READ or WRITE Q Q Configurable Routing Elements Programmable connection Programmable bypass Routing Resource #1 P Routing Resource #2 DFF OUT SIGNAL P Logic Elements P1 P2 P3 P4 P5 P6 P7 P8 a c b OUT 0 1 2 3 4 5 6 7 Look-Up Table (LUT) Essentially a very small memory Most common size is 4-input LUT (shown is 3-input) Logic Elements 0 1 0 1 1 0 0 1 a c b OUT 0 1 2 3 4 5 6 7 Look-Up Table (LUT) OUT = a XOR b XOR c abc OUT 000 0 001 1 010 0 011 1 100 0 101 1 110 0 111 1 Logic Elements Look-Up Table (LUT) OUT = ab + ac + bc 1 0 1 1 1 1 0 1 a c b OUT 0 1 2 3 4 5 6 7 abc OUT 000 1 001 0 010 1 011 1 100 1 101 1 110 0 111 1 Logic Elements Look-Up Table (LUT) Extremely flexible in implementing logic Larger and slower than just using gates P1 P2 P3 P4 P5 P6 P7 P8 a c b OUT 0 1 2 3 4 5 6 7 FPGA Logic Structure “Cell” or “logic block”: 1 or more LUTs (generally 4-input) At least one D flip-flop Possibly fast carry logic Connect several logic blocks to form circuit 4-LUT carry logic Cout Cin OUT DFF I1 I2 I3 I4 Xilinx 4000 Combinational Logic Block Xilinx 4000 FPGA Really much more than 4 CLB’s and 9 configurable . | ECE 551 Digital Design And Synthesis Fall ‘09 Digital Circuit Implementations: Standard Cell FPGA Custom Logic Administrative Matters HW6 Meeting (due today by 4:00PM) Now What? After synthesis, implement as hardware FPGAs Standard cells Custom logic Choose implementation based on cost and performance requirements FPGAs Field Programmable Gate Array Temporary (SRAM based) Permanent (Flash) not as common Pros Allow for very complex implementations Generally reuseable (upgrades/bugfixes/prototype) Low non-recurring engineering costs (NREs) Cons Expensive per-unit (10s-100s of $) Slower than gates Need support cirucuits (configuration loading) Not as robust (mission critical operations) Programming an FPGA Most designs based on SRAM Writing to the SRAM “configures” device Different circuits implemented based on values DATA READ or WRITE Q Q Configurable Routing Elements Programmable connection Programmable bypass Routing Resource #1 P Routing Resource #2 DFF OUT .

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 11
• ECE 551 Digital Design
• Programming an FPGA
• Configurable Routing Elements
• Standard Cell Layouts
• The Hardware Implementations
• Efficient Multiplication Methods
• Booth’s Multiplication Method
• A review of modular multiplication
• Respective Hardware Implementations
• The Multiplication algorithm
• Karatsuba Ofman Method
• Hardware implementation
• High throughput
• Power saving
• High efficiency video coding standard
• Coding hardware implementation
• Ant Colony
• Optimization Toward
• Feature Selection
• Hardware Implementations
• Algorithmic Models
• Graphics Processing Units