tailieunhanh - ECE 551 Digital Design And Synthesis: Lecture 6

ECE 551 Digital Design And Synthesis: Lecture 6 has many contents: while, repeat, forever loops, Loops in Verilog, Tasks in testbenches, Include Compiler Directives, Parallel blocks (fork/join), Named blocks (disabling of blocks), File I/O, Functions & Tasks,. | ECE 551 Digital Design And Synthesis Fall ‘09 Handy Testbench Constructs: while, repeat, forever loops Parallel blocks (fork/join) Named blocks (disabling of blocks) File I/O Functions & Tasks Administrative Matters Readings Chapter 7 (last part, if you haven’t read already) Chapter 8 (tasks & functions) Loops in Verilog We already saw the for loop: reg [15:0] rf[0:15]; // memory structure for modeling register file reg [5:0] w_addr; // address to write to for (w_addr=0; w_addr while loops Executes until boolean condition is not true If boolean expression false from beginning it will never execute loop reg [15:0] flag; reg [4:0] index; initial begin index=0; found=1’b0; while ((index repeat Loop Good for a fixed number of iterations Repeat count can be a variable but It is only evaluated when the loops starts If it changes during loop execution it won’t change the number of iterations Used in conjunction with @(posedge clk) it forms a handy & succinct way to wait in testbenches for a fixed number of clocks initial begin inc_DAC = 1’b1; repeat(4095) @(posedge clk); // bring DAC right up to point of rollover inc_DAC = 1’b0; inc_smpl = 1’b1; repeat(7)@(posedge clk); // bring sample count up to 7 inc_smpl = 1’b0; end forever loops We got a glimpse of this already with clock generation in testbenches. Only a $stop, $finish or a specific disable can end a forever loop. initial begin clk = 0; forever #10 clk = ~ clk; end Clock generator is by far the most common use of a forever loop Sequential vs Parallel . | ECE 551 Digital Design And Synthesis Fall ‘09 Handy Testbench Constructs: while, repeat, forever loops Parallel blocks (fork/join) Named blocks (disabling of blocks) File I/O Functions & Tasks Administrative Matters Readings Chapter 7 (last part, if you haven’t read already) Chapter 8 (tasks & functions) Loops in Verilog We already saw the for loop: reg [15:0] rf[0:15]; // memory structure for modeling register file reg [5:0] w_addr; // address to write to for (w_addr=0; w_addr while loops Executes until boolean condition is not true If boolean expression false from beginning it will never execute loop reg [15:0] flag; reg [4:0] index; initial begin index=0; found=1’b0; while ((index<16) && (!found)) begin if (flag[index]) found = 1’b1; else index = index + 1; end if (!found) $display(“non-zero flag bit not found!”); .

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 6
• ECE 551 Digital Design
• Loops in Verilog
• Loading Memory Data From Files
• Tasks in testbenches
• Include Compiler Directives