tailieunhanh - ECE 551 Digital Design And Synthesis: Lecture 5

ECE 551 Digital Design And Synthesis: Lecture 5 has many contents: Counters are Common, Pill Counter, Ring Counter (a better way), Aside (a quick intro to parameters), SM Interacting with SM, Shifters/Rotators, Parameters Proper SM Coding, Random Misc Stuff,. | ECE 551 Digital Design And Synthesis Fall ‘09 Counters are Common Shifters/Rotators Parameters Proper SM Coding Random Misc Stuff Administrative Matters Readings Cummings paramdesign paper for hdlcon (posted on class website) What Have We Learned? Sequential elements (flops & latches) should be inferred using non-blocking “ Engineers are paid to think, Pharmacists are paid to follow rules Counters are commonly needed blocks. 0 1 R +1 comb clk en rst_n cnt[7:0] 8-bit counter with reset & enable Increment logic & mux are combinational blocking Flop is seqential. non-blocking Pill Counter module pill_cnt(clk,rst_n,en,cnt); input clk,rst_n; output [7:0] cnt; reg [7:0] nxt_cnt,cnt; always @(posedge clk, negedge rst_n) if (!rst_n) cnt . Counter (the rebel engineer) module iq_cnt(clk,rst_n,en,cnt); input clk,rst_n; output [7:0] cnt; reg [7:0] cnt; always @(posedge clk or negedge rst_n) if (!rst_n) cnt Ring Counter module ring_counter (count, enable, clock, reset); output reg [7: 0] count; input enable, reset, clock; always @ (posedge | ECE 551 Digital Design And Synthesis Fall ‘09 Counters are Common Shifters/Rotators Parameters Proper SM Coding Random Misc Stuff Administrative Matters Readings Cummings paramdesign paper for hdlcon (posted on class website) What Have We Learned? Sequential elements (flops & latches) should be inferred using non-blocking “ Engineers are paid to think, Pharmacists are paid to follow rules Counters are commonly needed blocks. 0 1 R +1 comb clk en rst_n cnt[7:0] 8-bit counter with reset & enable Increment logic & mux are combinational blocking Flop is seqential. non-blocking Pill Counter module pill_cnt(clk,rst_n,en,cnt); input clk,rst_n; output [7:0] cnt; reg [7:0] nxt_cnt,cnt; always @(posedge clk, negedge rst_n) if (!rst_n)