tailieunhanh - ECE 551 ModelSim Tutorial

In this tutorial, you will learn how to setup a ModelSim project, compile your Verilog files, correct compilation errors, and perform design debugging using ModelSim. The example design used within this tutorial is simple Synchronous Serial Port (SSP) that contains both a send and receive module. | ECE 551 ModelSim Tutorial Brian Hickmann Michael Morrow co-opted tweaked for Hoffman Nalamalpu Dept of ECE UW-Madison In this tutorial you will learn how to setup a ModelSim project compile your Verilog files correct compilation errors and perform design debugging using ModelSim. The example design used within this tutorial is simple Synchronous Serial Port SSP that contains both a send and receive module. It has a simple 3-wire interface Port Name Function SerData Bi-directional data line used for both sending and receiving Recv_nTran Input that indicates if we are receiving 1 or transmitting 0 StartOp Input that indicates that an operation should be performed The design of this unit is broken into a number of separate modules Module Name Function ssp Top-level module which instantiates all of the below sub-modules receive Contains the shift register and state machine for the receiver transmit Contains the shift register and state machine for the transmitter busint Contains the logic to control the three wire serial interface The tutorial also contains testbenches for the receive transmit and ssp modules. The ModelSim Tutorial must be run on a Linux workstation using your CAE account in order to use the latest release of ModelSim version . IMPORTANT NOTE It is critical to remember that Verilog is NOT a software language. Verilog is used to describe hardware. While ModelSim may provide the ability to step through the code or insert breakpoints this is NOT what actually happens when the hardware is operating. In reality hardware is inherently parallel with each transistor or gate continuously providing an output signal based upon its input signals. For example in software if there is an if flag a b c else a b c statement only one branch of the statement is actually executed. However if HDL code has an if-else statement hardware must be created for both branches if the value of flag isn t constant. When we synthesize to hardware both an AND gate and an OR gate .

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