tailieunhanh - Quartus ® II Introduction for Verilog Users

This tutorial presents an introduction to the Quartus ® II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices, and shows how this flow is realized in the Quartus ® II software. The design process is illustrated by giving step-by-step instructions for using the Quartus ® II software to implement a simple circuit in an Altera ® FPGA device. | Quartus II Introduction for Verilog Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software. The design process is illustrated by giving step-by-step instructions for using the Quartus II software to implement a simple circuit in an Altera FPGA device. The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. This tutorial makes use of the Verilog design entry method in which the user specifies the desired circuit in the Verilog hardware description language. Another version of this tutorial is available that uses VHDL hardware description language. The screen captures in the tutorial were obtained using Quartus II version if other versions of the software are used some of the images may be slightly different. Contents Getting Started Starting a New Project Design Entry Using Verilog Code Compiling the Verilog Code Using the RTL Viewer Specifying Timing Constraints Quartus II Windows Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a programmable logic device such as a field-programmable gate array FPGA chip. A typical FPGA CAD flow is illustrated in Figure 1. Figure 1 Typical CAD flow. It involves the following basic steps Design Entry - the desired circuit is specified either by using a hardware description language such as Verilog or VHDL or by means of a schematic diagram Synthesis - the CAD Synthesis tool synthesizes the circuit into a netlist that gives the logic elements LEs needed to realize the circuit and the connections between the LEs Functional Simulation - the synthesized circuit is tested to verify its functional correctness the simulation does not take into account any timing issues Fitting - the CAD Fitter tool determines