tailieunhanh - Efficient Hardware Architectures for Modular Multiplication

This thesis describes the research which I conducted while completing my graduate work at the University of Applied Sciences Offenburg, Germany. The work produced scalable hardware implementations of existing and newly proposed algorithms for performing modular multiplication. | Efficient Hardware Architectures for Modular Multiplication by David Narh Amanor A Thesis submitted to The University of Applied Sciences Offenburg Germany In partial fulfillment of the requirements for the Degree of Master of Science in Communication and Media Engineering February 2005 Approved Prof. Dr. Angelika Erhardt Thesis Supervisor Prof. Dr. Christof Paar Thesis Supervisor Declaration of Authorship I declare in lieu of an oath that the Master thesis submitted has been produced by me without illegal help from other persons. I state that all passages which have been taken out of publications of all means or unpublished material either whole or in part in words or ideas have been marked as quotations in the relevant passage. I also confirm that the quotes included show the extent of the original quotes and are marked as such. I know that a false declaration will have legal consequences. David Narh Amanor February 2005 ii Preface This thesis describes the research which I conducted while completing my graduate work at the University of Applied Sciences Offenburg Germany. The work produced scalable hardware implementations of existing and newly proposed algorithms for performing modular multiplication. The work presented can be instrumental in generating interest in the hardware implementation of emerging algorithms for doing faster modular multiplication and can also be used in future research projects at the University of Applied Sciences Offenburg Germany and elsewhere. Of particular interest is the integration of the new architectures into existing publickey cryptosystems such as RSA DSA and ECC to speed up the arithmetic. I wish to thank the following people for their unselfish support throughout the entire duration of this thesis. I would like to thank my external advisor Prof. Christof Paar for providing me with all the tools and materials needed to conduct this research. I am particularly grateful to . Jan Pelzl who worked with me closely and .

• An ninh - Bảo mật
• The Modular Multiplication
• The Software Implementation
• The Hardware Implementation
• Results of the Architectures
• Analysis of the Architectures
• Efficient Hardware Architectures
• Efficient Multiplication Methods
• Booth’s Multiplication Method
• A review of modular multiplication
• Respective Hardware Implementations
• The Multiplication algorithm
• Karatsuba Ofman Method
• Carry save adder
• Sign estimation technique
• The Sign Estimation Technique
• The Modular Reduction Algorithm
• Implementation and Application
• Cryptographic Hardware and Embedded Systems
• The Embedded Systems
• The Cryptographic Hardware
• Modular multiplication in hardware
• XTR Implementation on Reconfigurable Hardware
• Secure the computer