tailieunhanh - Implementation of DES Algorithm Using FPGA Technology

The goal of this project is to continue the work of a student who worked on a pipelined VHDL implementation of the DES algorithm. Two architectures are studied for this project: one which is the fastest possible and another one which results in the less area than the first architecture on the FPGA. The meaning of speed for this project is the throughput (number of bits processed per second) and the meaning of area is number of CLB’s. | School of Computer and Communication Sciences Communication systems section ------------------------------------------ POEYTICHNIQyi IỂDÉRALE DE LAUSANNE Microelectronic Systems Laboratory 2002 Winter Semester Project Using FP1 Student Assistant Professor Arnaud Lagger Ilhan Hatirnaz Yusuf Leblebici Semester project Implementation of DES Algorithm Using FPGA Technology Arnaud Lagger INTRODUCTION 4 OVERVIEW OF CRYPTOGRAPHY 5 Symmetric-key encryption 5 Data encryption Standard DES 6 Examples of modern equipments which use DES encryption 11 METHOD 12 Tools 12 Software 12 Hardware 12 Design flow 14 UNDERSTANDING THE CODE 16 Components 17 desenc 17 keysched 17 IP 17 roundfunc 18 FP 18 FAST DESIGN 19 Optimizations 19 Simulation proces s 21 Synthesis process 22 Place route 25 FPGA 26 SMALL DESIGN 27 Simulation process 30 Synthesis process 31 Place route 32 FPGA 33 CONCLUSION 34 ACKNOWLEDGEMENTS 35 REFERENCES 36 Books and articles 36 Web sites 36 APPENDIXES 37 Figures for fast design 37 Figure la 37 Figure 2a 38 Figure 3a 39 Figure 4a 40 Figure 5a 4l Figure 6a 42 Figures for small design 43 Figure lb 43 Figure 2b 44 Figure 3b 45 Figure 4b 46 Figure 5b 47 Excerpts of the VHDL code 48 -2- Semester project Implementation of DES Algorithm Using FPGA Technology Arnaud Lagger Fast design Small design 48 .