tailieunhanh - Báo cáo hóa học: " Generic Hardware Architectures for Sampling and Resampling in Particle Filters"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Generic Hardware Architectures for Sampling and Resampling in Particle Filters | EURASIP Journal on Applied Signal Processing 2005 17 2888-2902 2005 Hindawi Publishing Corporation Generic Hardware Architectures for Sampling and Resampling in Particle Filters Akshay Athalye Department of Electrical and Computer Engineering Stony Brook University Stony Brook NY 11794-2350 USA Email athalye@ Miodrag Bolic Department of Electrical and Computer Engineering Stony Brook University Stony Brook NY 11794-2350 USA Email mbolic@ Sangjin Hong Department of Electrical and Computer Engineering Stony Brook University Stony Brook NY 11794-2350 USA Email snjhong@ Petar M. Djuric Department of Electrical and Computer Engineering Stony Brook University Stony Brook NY 11794-2350 USA Email djuric@ Received 18 June 2004 Revised 11 April 2005 Recommended for Publication by Markus Rupp Particle filtering is a statistical signal processing methodology that has recently gained popularity in solving several problems in signal processing and communications. Particle filters PFs have been shown to outperform traditional filters in important practical scenarios. However their computational complexity and lack of dedicated hardware for real-time processing have adversely affected their use in real-time applications. In this paper we present generic architectures for the implementation of the most commonly used PF namely the sampling importance resampling filter SIRF . These provide a generic framework for the hardware realization of the SIRF applied to any model. The proposed architectures significantly reduce the memory requirement of the filter in hardware as compared to a straightforward implementation based on the traditional algorithm. We propose two architectures each based on a different resampling mechanism. Further modifications of these architectures for acceleration of resampling process are presented. We evaluate these schemes based on resource usage and latency. The platform used for the evaluations is the .