tailieunhanh - Báo cáo hóa học: " A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs | EURASIP Journal on Applied Signal Processing 2003 6 555-564 2003 Hindawi Publishing Corporation A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs Alex Carreira Department of Electrical and Computer Engineering University of Calgary 2500 University Drive . Calgary Alberta Canada T2N1N4 Email aycarrei@ TrevorW. Fox Department of Electrical and Computer Engineering University of Calgary 2500 University Drive Calgary Alberta Canada T2N1N4 Email fox@ ca Laurence E. Turner Department of Electrical and Computer Engineering University of Calgary 2500 University Drive . Calgary Alberta Canada T2N1N4 Email turner@ Received 28 February 2002 and in revised form 17 October 2002 Area-efficient peak-constrained least-squares PCLS bit-serial finite impulse response FIR filter implementations can be rapidly prototyped in field programmable gate arrays FPGA with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio PSR performance to be traded for a reduction in the filter s hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods. Keywords and phrases placement mapping FIR filter PCLS bit serial JBits. 1. INTRODUCTION Finite duration impulse response FIR digital filters are .