tailieunhanh - Data Acquisition Part 15

Tham khảo tài liệu 'data acquisition part 15', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | High-Efficiency Digital Readout Systems for Fast Pixel-Based Vertex Detectors 341 that have been designed to stand a 12 Gbit s input rate Gbit s output rate and have the possibility to perform different types of trigger strategies on data. The most important one was the on-line track identification performed with the help of an Associative Memory board G. Batingani et Al. year 2008 which demonstrated the capability of the setup to trigger on identified tracks with a minimal latency lự s . The EDRO board is based on FPGAs Field Programmable Gate Arrays a picture is presented in Fig. 26. The acronym stands for Event Dispatch and Read Out. It is a 9U VME master board holding 5 mezzanine boards mounted on piggy-back. It is capable of an integrated input output of 30 Gbps. Gbit s Gbiưs Fig. 26. EDRO board picture. Event Dispatch and ReadOut . A TTCrq mezzanine card . Taylor 2005 developed for LHC experiments has been used as a 40 MHz clock source. Two Programmable Mezzanine Cards EPMC are responsible for the communication to from the front-end chips. They host an Altera Cyclone II FPGA in a BGA package and several LVTTL LVDS converters for the communication to from the front-end Each EPMC can handle 2 Apsel4D chips. The limit is imposed by the high number of I O required by the AREO architecture rather than the front-end data rate since each EPMC can handle up to Gbps. Internal logic and most of the on-board data transfer run at 120 MHz clock ensuring a data input output of the order of GBit s. The hits collected from the EPMCs are forwarded 4 Differential signaling is used on the 30 m cable that connect the EDRO board to the electronics in the experimental area. There the signals are converted back to single ended CMOS to be connected to the aPsEL4D digital I O 342 Data Acquisition to the main mezzanine of the EDRO board an 18 layers board holding an Altera Stratix II FPGA with 1508 pins developed for the CMS muon finder J. Ero et Al. .

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