tailieunhanh - Báo cáo hóa học: "A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study | Hindawi Publishing Corporation EURASIP Journal on Applied Signal Processing Volume 2006 Article ID 89186 Pages 1-12 DOI ASP 2006 89186 A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study Abbas Bigdeli Morteza Biglari-Abhari Zoran Salcic and Yat Tin Lai Department of Electrical and Computer Engineering the University of Auckland Private Bag 92019 Auckland New Zealand Received 11 November 2004 Revised 20 June 2005 Accepted 12 July 2005 A new pipelined systolic array-based PSA architecture for matrix inversion is proposed. The pipelined systolic array PSA architecture is suitable for FPGA implementations as it efficiently uses available resources of an FPGA. It is scalable for different matrix size and as such allows employing parameterisation that makes it suitable for customisation for application-specific needs. This new architecture has an advantage of O n processing element complexity compared to the O n2 in other systolic array structures where the size of the input matrix is given by n X n. The use of the PSA architecture for Kalman filter as an implementation example which requires different structures for different number of states is illustrated. The resulting precision error is analysed and shown to be negligible. Copyright 2006 Hindawi Publishing Corporation. All rights reserved. 1. INTRODUCTION Many DSP algorithms such as Kalman filter involve several iterative matrix operations the most complicated being matrix inversion which requires O n3 computations n is the matrix size . This becomes the critical bottleneck of the processing time in such algorithms. With the properties of inherent parallelism and pipelining systolic arrays have been used for implementation of recurrent algorithms such as matrix inversion. The lattice arrangement of the basic processing unit in the systolic array is suitable for executing regular matrix-type computation. Historically systolic arrays have been widely .