tailieunhanh - Báo cáo hóa học: " Research Article Geometry Unit for Analysis of Warped Image Features on Programmable Chips"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Geometry Unit for Analysis of Warped Image Features on Programmable Chips | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2007 Article ID 37317 8 pages doi 2007 37317 Research Article Geometry Unit for Analysis of Warped Image Features on Programmable Chips Johannes Furtler 1 Konrad J. Mayer 1 Christian Eckel 2 Jorg Brodersen 1 Herbert Nachtnebel 3 and Gerhard Cadek2 1 Business Unit of High Performance Image Processing Austrian Research Centers Gmbh-ARC 2444 Seibersdorf Austria 2 Oregano Systems - Design and Consulting GmbH Phorusgasse 8 1040 Vienna Austria 3 Institute of Computer Technology Vienna University of Technology Gufhausstrafe 27-29 E384 1040 Vienna Austria Received 1 May 2006 Revised 13 October 2006 Accepted 30 October 2006 Recommended by Udo Kebschull Among many constraints applicable for embedded visions systems in industrial applications desired processing performance is a determining factor of system costs. For technically and economically successful solutions it is essential to match algorithms and architecture. High-end field programmable gate arrays open the perspective to vision systems on a programmable chip leading to reduced size and higher performance. The architecture proposed in our previous publications in 2004 and 2006 is based on reusable building blocks. This paper continues with a particular building block for backward warping and interpolation of arbitrary shaped image regions which can be used for many image processing tasks including image statistics projections and template matching. The architecture is discussed and a typical application for template matching is presented. The suggested unit serves as universal basis for high-level image processing implemented on programmable chips which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units. Copyright 2007 Johannes Furtler et al. This is an open access article distributed under the Creative Commons Attribution License which