tailieunhanh - Xilinx VHDL Test Bench Tutorial

This tutorial will guide you through the process of creating a test bench for your VHDL designs, which will aid you in debugging your design before or in addition going to the FPGA for execution. For the sake of simplicity, we will revisit the counter tutorial available at Professor Duckworth’s website: . We will recreate the sample counter and decoder and then create a VHDL test bench for the counter to show what it looks like in the new Xilinx software. This process will be helpful to you in the later labs in the course, as you will be able. | Xilinx VHDL Test Bench Tutorial Billy Hnath bhnath@ Department of Electrical and Computer Engineering Worcester Polytechnic Institute Revision Introduction This tutorial will guide you through the process of creating a test bench for your VHDL designs which will aid you in debugging your design before or in addition going to the FPGA for execution. For the sake of simplicity we will revisit the counter tutorial available at Professor Duckworth s website http rjduck Nexys2 20ISE 2010 1 20Counter . We will recreate the sample counter and decoder and then create a VHDL test bench for the counter to show what it looks like in the new Xilinx software. This process will be helpful to you in the later labs in the course as you will be able to see what your signals are doing as well as allow you to check to see if the values coming out are correct or not. Without further ado - let us continue to the counter example. The Simple 4-bit Counter Revisited If you have already created a project for the counter tutorial feel free to use that as a base for this tutorial. If you have not please follow the tutorial at the link given in the introduction to complete the counter design. With the counter and decoder designs created and synthesized select from the Xilinx tool bar Project - New Source. Name the source something that signifies it s a test bench such as counter_tb in this example. Click Next . From here select which design you want to create a test bench for. Here we will select the counter design as it is at the top-level for this project. Keep in mind that you may make test benches for individual components of your designs as well as the top-level design which ties it all together analogous to testing individual functions versus your main in a programming language . Click Next . Select Finish

• Kỹ thuật lập trình
• The Simple 4 bit
• VHDL Test BenchInternal Signal Watching
• Upping the Clock Speed
• VHDL Counter Tutorial
• ISE Simulator