tailieunhanh - Parallel Programming: for Multicore and Cluster Systems- P16

Parallel Programming: for Multicore and Cluster Systems- P16: Innovations in hardware architecture, like hyper-threading or multicore processors, mean that parallel computing resources are available for inexpensive desktop computers. In only a few years, many standard software products will be based on concepts of parallel programming implemented on such hardware, and the range of applications will be much broader than that of scientific computing, up to now the main application area for parallel computing | Further Parallel Programming Approaches 141 Memory Access Times and Cache Effects Memory access times may constitute a significant portion of the execution time of a parallel program. A memory access issued by a program causes a data transfer from the main memory into the cache hierarchy of that core which has issued the memory access. This data transfer is caused by the read and write operations of the cores. Depending on the specific pattern of read and write operations not only is there a transfer from main memory to the local caches of the cores but there may also be a transfer between the local caches of the cores. The exact behavior is controlled by hardware and the programmer has no direct influence on this behavior. The transfer within the memory hierarchy can be captured by dependencies between the memory accesses issued by different cores. These dependencies can be categorized as read-read dependency read-write dependency and write-write dependency. A read-read dependency occurs if two threads running on different cores access the same memory location. If this memory location is stored in the local caches of both cores both can read the stored values from their cache and no access to main memory needs to be done. A read-write dependency occurs if one thread T1 executes a write into a memory location which is later read by another thread T2 running on a different core. If the two cores involved do not share a common cache the memory location that is written by T1 must be transferred into main memory after the write before T2 executes its read which then causes a transfer from main memory into the local cache of the core executing T2. Thus a read-write dependency consumes memory bandwidth. A write-write dependency occurs if two threads T1 and T2 running on different cores perform a write into the same memory location in a given order. Assuming that T1 writes before T2 a cache coherency protocol see Sect. must ensure that the caches of the

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