tailieunhanh - Handbook of algorithms for physical design automation part 64

Handbook of Algorithms for Physical Design Automation part 64 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 612 Handbook of Algorithms for Physical Design Automation In general the accuracy of placement-based metrics decreases as the level of abstraction of the netlist increases. Indeed almost all the metrics proposed for use during logic synthesis to date are graph theoretic in nature. With the problem of routing congestion getting worse because of the scaling of design sizes and process technologies a comprehensive congestion management strategy must target congestion through the entire design flow relying on the appropriate congestion estimators at each stage. The interested reader can find further details on all the metrics discussed in this chapter in the corresponding papers or in Ref. SSS07 . REFERENCES CZY 99 Chen H. -M. Zhou H. Young F. Y. Wong D. F. Yang H. H. and Sherwani N. Integrated floorplanning and interconnect planning Proceedings of the International Conference on Computer-Aided Design San Jose CA pp. 354-357 1999. Che94 Cheng C. -L. E. Risa Accurate and efficient placement routability modeling Proceedings of the International Conference on Computer-Aided Design San Jose CA pp. 690-695 1994. CL00 Cong J. and Lim S. Edge separability based circuit clustering with application to circuit partitioning Proceedings of the Asia and South Pacific Design Automation Conference Yokohama Japan pp. 429-434 2000. Dai01 Dai W. Hierarchial physical design methodology for multi-million gate chips Proceedings of the International Symposium on Physical Design Sonoma CA pp. 179-181 2001. HNR68 Hart P. E. Nilsson N. J. and Raphael B. A formal basis for the heuristic determination of minimum cost paths IEEE Transactions on System Science and Cybernetics SSC-4 pp. 100-107 1968. HB97 Hauck S. and Borriello G. An evaluation of bipartitioning techniques IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16 8 849-866 August 1997. ARVLSI 1995 . Hig69 Hightower D. W. A solution to line routing problems on the continuous plane Proceedings of the Design .