tailieunhanh - Handbook of algorithms for physical design automation part 103

Handbook of Algorithms for Physical Design Automation part 103 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 1002 Handbook of Algorithms for Physical Design Automation 29. Y. -S. Kwon P. Lajevardi A. P. Chandrakasan F. Honoré and D. E. Troxel. A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. In Proceedings of the 2005 International Workshop on System Level Interconnect Prediction SLIP San Francisco CA pp. 65-72 2005. 30. M. Alexander J. Cohoon J. Colflesh J. Karro E. Peters and G. Robins. Placement and routing for threedimensional FPGAs. In Fourth Canadian Workshop on Field-Programmable Devices Toronto Canada pp. 11-18 1996. 31. J. Karro and J. P. Cohoon. A spiffy tool for the simultaneous placement and global routing for threedimensional field-programmable gate arrays. In Proceedings of the Great Lakes Symposium on VLSI Ann Arbor MI pp. 230-231 1999. 32. C. Ababei H. Mogal and K. Bazargan. Three-dimensional place and route for FPGAs. IEEE Transactions on Computer-Aided Design 25 6 1132-1140 June 2006. 33. V. Betz and J. Rose. VPR A new packing placement and routing tool for FPGA research. In Field-Programmable Logic and Applications London . pp. 213-222 1997. 34. G. Karypis R. Aggarwal V. Kumar and S. Shekhar. Multi-level hypergraph partitioning Applications in VLSI design. In Proceedings of the ACM IEEE Design Automation Conference Anaheim CA pp. 526-529 1997. 35. P. Maidee C. Ababei and K. Bazargan. Fast timing-driven partitioning-based placement for island style FPGAs. In Proceedings of the ACM IEEE Design Automation Conference Anaheim CA pp. 598-603 2003. 36. C. Ababei Y. Feng B. Goplen H. Mogal T. Zhang K. Bazargan and S. Sapatnekar. Placement and routing in 3D integrated circuits. IEEE Design and Test 22 6 520-531 November-December 2005. 37. B. Goplen and S. S. Sapatnekar. Placement of thermal vias in 3-D ICs using various thermal objectives. IEEE Transactions on Computer-Aided Design 26 4 692-709 April 2006. Index A Amplitude and intensity for conventional mask 709 Absorption metric role of 114 Abutment constraints 172