tailieunhanh - Handbook of algorithms for physical design automation part 101

Handbook of Algorithms for Physical Design Automation part 101 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 982 Handbook of Algorithms for Physical Design Automation Source Switchbox FIGURE Three critical path configurations and delay variations of a switch matrix. Based on Matsumoto Y. et al. Proceedings of the 2007 ACM SIGDA 15th International Symposium on Field Programmable Gate Arrays ACM Press New York 2007. With permission. where Y1 Target is defined as Yi Target J fa t dt œ In Equation the likelihood that all n configurations fail is subtracted from 1. In their work they assume complete independence between critical paths in different configurations which enables them to analytically evaluate Equations and . This assumption is not valid as we know spatial correlations exist between circuit elements and also critical paths across different configurations might share routing resources especially close to the source and sink nodes. They propose a routing algorithm that keeps track of the usage of routing resources by critical paths and tries to avoid them in consecutive configurations that are generated. The method is similar to the congestion avoidance procedure used in VPR that is resources that are used by critical paths in other configurations are penalized so that the router avoids them if other paths with the same delay exist. REFERENCES 1. J. Cong and K. Minkovich Optimality study of logic synthesis for Lut-based FPGAs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26 2 230-239 2007. 2. D. Chen and J. Cong Daomap A depth-optimal area optimization mapping algorithm for FPGA designs in ICCAD 04 Proceedings of the 2004 IEEE ACM International Conference on Computer-Aided Design pp. 752-759 IEEE Computer Society Washington DC 2004. 3. B. L. Synthesis and V. Group Abc A system for sequential synthesis and verification. Available at http . berkeley. edu alanmi abc . 4. Alan S. Chatterjee and R. Brayton Improvements to technology mapping for Lut-based FPGAs in FPGA 06 Proceedings of the 2006 ACM SIGDA