tailieunhanh - Handbook of algorithms for physical design automation part 59

Handbook of Algorithms for Physical Design Automation part 59 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 562 Handbook of Algorithms for Physical Design Automation algorithm enhancements it is shown how to choose technology constants how to trade off wirelength and slack and how to deal with blockages congestion and high fanout nets. Experimental results demonstrate that generated trees are of good quality and that the algorithm execution time is extremely small one million trees are computed in less than a minute note that if a robust buffer insertion is needed additional CPU time may be required for postprocess buffering . SIMULTANEOUS TREE CONSTRUCTION AND BUFFER INSERTION In this section some of the methods that combine buffer insertion and topology construction are presented. Most of them belong to the P-Tree class of algorithms. The work started with the first version of the P-Tree algorithm 8 that was designed to construct timing-driven routing tree and it has seen a decade long evolution of various improvements and extensions that were building on the original ideas. These algorithms are designed to handle a variety of challenges seen in modern designs. Simultaneous tree construction and repeater insertion with multiple buffers and inverters in the library while being able to optimize multiple objectives again simultaneously delay cost congestion wirelength are achieved through the core optimization engine. Practical issues such as obstacles . placement and routing blockages multilayer routing and vias and nonorthogonal routing are handled by the capability of the algorithms to work on general graph models as routing targets. Spatial temporal and polarity localities all of them independently are captured and exploited by implicit specification of the set of tree topologies that will be searched. In the following subsections we give an overview of the mentioned contributions in chronological order. P-Tree Algorithm The work in Ref. 8 presents an algorithm that constructs rectilinear Steiner trees while explicitly optimizing both delay and wire .