tailieunhanh - Handbook of algorithms for physical design automation part 35

Handbook of Algorithms for Physical Design Automation part 35 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 322 Handbook of Algorithms for Physical Design Automation annealing is performed where the range of cell movement is limited and the number of moves per cell is greatly reduced thereby the overall execution time is reduced. This resulted in a factor of 2-3 speedup in execution time and a 6-17 percent improvement in half-perimeter wirelength. Sun and Sechen increased the number of levels of clustering to three 15 . They were able to achieve up to x speedup on designs containing 25 000 placeable objects. They also saw an improvement in half-perimeter wirelength due to clustering although some of the improvement may be due to their new cost function and wire estimation model. In this work the cost function used only contained the sum of the half-perimeter wirelengths and timing constraints. All penalty functions were removed so that there would be no need for the sophisticated negative feedback controller used to weigh the penalty terms. Instead only moves that generated no overlap were allowed. PARTITION-BASED METHODS Simulated annealing placers have also incorporated partitioning techniques to achieve better quality and speed. NRG 24 and Tomus 25 convert the placement problem to a partitioning problem that is solved using simulated annealing. The placement problem is reduced by dividing the row topology into uniform grids or bins. Each standard cell or field programmable gate array lookup table FPGA LUT is assigned to a bin. A penalty term is introduced to maintain uniform cell density among the bins. Standard cells are exchanged by picking two cells in different bins and swapping them. Because the number of bins is much smaller than the possible standard cell positions the search space is reduced resulting in a speedup. A second or detailed placement phase ensues which removes any residual overlap and legalizes the placement of the cells. Both of these algorithms worked on a flat netlist and did not scale well for larger netlists. The NRG work was enhanced