tailieunhanh - Handbook of algorithms for physical design automation part 7

Handbook of Algorithms for Physical Design Automation part 7 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 42 Handbook of Algorithms for Physical Design Automation NOISE Coupling noise is yet another unwanted side effect of the scaling in deep submicron technology and its impact can be reduced through physical design transformations. The effect arises due to geometric scaling which requires the wires to be narrower and the spacing between adjacent wires smaller. On the other hand because the chip size is also getting larger in terms of multiples of the minimum feature size it is necessary to reduce wire resistance by increasing the aspect ratio of the wire cross section. The compounded effect is the increase of the coupling capacitance between adjacent signal wires. When two interconnect networks are capacitively coupled usually the one with the stronger driving gate is referred to as the aggressor while the one with the weaker driver is called the victim. It is quite possible that an aggressor can affect multiple victims and a victim can have more than one aggressors. For simplicity we only discuss the case with one aggressor and one victim. These ideas can be easily extended to more general cases. The application domain for this analysis is in noise-aware routing. For scalable methods that can be applied to full-chip noise analysis the reader is referred to Chapter 34. When the aggressor switches if the victim is quiet then the coupling will generate a glitch on the victim wire. If the glitch is sufficiently large and occurs within a certain timing window the erroneous glitch can be latched into a memory storage element and cause a logic error. If the victim is also switching then depending on the polarities of the signals and the corresponding switching windows the signal on the victim wire can be slowed down or sped up which may cause timing violations. Although very elaborate algorithms are available to estimate the coupling effects between the signal wires see Refs. 9 10 it is highly desirable to correct the problem at its root . during the physical design