tailieunhanh - Báo cáo "Another method of logic synthesis of digital counting circuits "

In order to synthesize automat (in this case digital counters), the minimizing internal states is of particular significance and plays a decisive role in the results of synthetic circuit. This can be done in many ways, but the use of Karnaugh map is considered optimal. However, this process has some disadvantages that it can not be overcome when the number of input variants is large. In experience, if the number of variants is 7, manual minimization of circuit functions using Karnaugh map arises many difficulties and even become impossible if over 10 variants are available. In order to deal. | VNU. JOURNAL OF SCIENCE Mathematics - Physics N03 2005 ANOTHER METHOD OF LOGIC SyNTHESIS OF DIGITAL COUNTING CIRCUITS Nguyen Quy Thuong Vietnam National University Hanoi Abstract. In order to synthesize automat in this case digital counters the minimizing internal states is of particular significance and plays a decisive role in the results of synthetic circuit. This can be done in many ways but the use of Karnaugh map is considered optimal. However this process has some disadvantages that it can not be overcome when the number of input variants is large. In experience if the number of variants is 7 manual minimization of circuit functions using Karnaugh map arises many difficulties and even become impossible if over 10 variants are available. In order to deal with this weakness it is both necessary and rational to use computer in logical synthesis of counting circuit. This is the aim of this article. 1. Synthesizing counting circuits using similar forms For the method of synthesizing digital counting circuits using computers is firstly primarily based on the results achieved through the Karnaugh map 1 . By there results drawning the general laws of circuit functions for each synchronous and asynchronous counters for each Flip-Flop FF and for each kind of codes. These general laws help to develop mathematical models as well as computer programmes which enable the fastest definition of minimized circuit functions of each desired counters. Let us investigate for example the input states R2 S2 and outputs states Q2 of RS FF in synchronous counters real binary 4 inputs k 4 . The input states R2 S2 as well as outputs states Q2 are given in table 1. Table 1. The input states R2 S2. s is counting state s 2k 1 24- 1 15 m -1 with m is a cardinal number Q2 is an output state corresponding inputs states S2 and R2 8 Q2 R2 S2 8 Q2 R2 S2 8 Q2 R2 S2 8 Q2 R2 S2 0 0 d 0 4 0 d 0 8 0 d 0 12 0 d 0 1 0 0 1 5 0 0 1 9 0 0 1 13 0 0 1 2 1 0 d 6 1 0 d 10 1 0 d 14 1 0 d 3 1 1 0 7 1 1 0

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