tailieunhanh - Current Trends and Challenges in RFID Part 4

Tham khảo tài liệu 'current trends and challenges in rfid part 4', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 80 Current Trends and Challenges in RFID 2. Minimum emitter area for matched transistors otherwise there will be a degradation in the current gain P 3. Guard ring around the base to ensure that electrostatics charges will not influence the current flow in the neutral base 4. Use of multiple collectors for lateral PNP transistors. A moderate match can be reached when the collectors are identical and out of the saturation condition 5. The matched transistors should be close to each other in order to minimize the impact of the thermal gradient. 6. The matched transistors should be placed in gradients lines of minimum stress 7. The transistor must be aligned with the wafer axis 8. Place as many metal contacts as possible in the emitter following the emitter geometry to reduce the contact resistance and to distribute the current flow uniformly 9. Use emitter degeneration. Lateral PNP transistors are often more benefited with emitter degeneration compared to the NPN vertical counterparts due to the Early voltage and the large emitter area. They are commonly used in current mirrors. The matching over integrated components reflects the overall performance of the entire circuit or system. Depending on the matching accuracy the circuits may present 1. Minimum In the range of 1 representing 6 to 7 bits of resolution . Used for general use components in an analog circuit such as current mirrors and biasing circuits 2. Moderate In the range of representing 9 to 10 bits of resolution . Used in bandgap references operational amplifiers and input stage of voltage comparators. This range is the most appropriate for analog designs. 3. Severe In the range of representing 13 t0 14 bits of resolution . Used in high precision analog to digital converters ADCs and digital to analog converters DACs . Analog designs that use capacitors ratio reach this range easer then those that using resistors ratios. Figure 26 shows an example of a PNP vertical bipolar transistor layout. Fig. .