tailieunhanh - The MEMS Handbook (1st Ed) - M. Gad el Hak Part 11

Tham khảo tài liệu 'the mems handbook (1st ed) - m. gad el hak part 11', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | High-temperature metallization n -type 6H-SÌC piezoresistors Oxide p-type 6H-SiC etch-stop epilayer n-type 6H-SiC substrate Outline of diaphragm Longitudinal piezoresistors all radially oriented n-type 6H-SĨC o High-temperature metallization o SiO2 FIGURE a Cross-section view of 6H-SÌC after PECS of the top n -epilayer and ECE of the backside cavity. Notice the curvature in the cavity which is characteristic of the ECE process. b Top view of patterned piezoresistors in n-type 6H-SiC. another appropriate mask such as polyimide or polyimide on silicon nitride anodization reaction will only occur at the appropriate areas. The polyimide can prevent the pinhole formation while the silicon nitride can minimize the effect of undercutting. Polyimide is highly conformal and therefore will plug the pinholes. Silicon nitride is not conductive and is therefore electrically and chemical inactive during PECE. One effective method used to neutralize pinholes in platinum is by double-layer deposition. After the deposition of the first platinum layer the film is sputter-etched and subsequently a second platinum layer is deposited. This significantly reduces pinhole formation and pitting associated with the platinum etch mask. In many cases the p-type SiC layer is not a fully effective etch-stop. This effect was observed in p-type SiC with low doping levels Na 1018cm 3 . Apparently in lightly doped material the electric field in the space-charge region is not high enough to prevent all the photogenerated carriers from reaching the surface to cause etching. In addition the UV light incident on the n-p junction causes higher leakage currents across the junction than higher doped p-type SiC. Although the anodic voltage is applied only through the ohmic contact on the top n-type SiC epilayer the light-induced current through the junction leads to etching of the p-type SiC. To avoid etching of the p-type SiC epilayer the reference voltage VSCE must be reduced to a level that .