tailieunhanh - SystemVerilog For Design phần 2

Trực tiếp khai báo các đối tượng trong các đơn vị biên soạn, đơn vị không gian có thể dẫn đến thiết kế các lỗi khi các tập tin được biên dịch riêng. Nó cũng có thể dẫn đến mã Spaghetti nếu khai báo nằm rải rác trong nhiều tập tin có thể được khó khăn để duy trì, tái sử dụng, hoặc để gỡ lỗi các lỗi kê khai. | Chapter 2 SystemVerilog Declaration Spaces 17 Coding guidelines unit should 1. only be used for importing packages 2. Do not make any declarations in the unit space All declarations should be made in named packages. When necessary packages can be imported into unit. This is useful when a module or interface contains multiple ports that are of user-defined types and the type definitions are in a pack- age. Directly declaring objects in the unit compilation-unit space can lead to design errors when files are compiled separately. It can also lead to spaghetti code if the declarations are scattered in multiple files that can be difficult to maintain re-use or to debug declaration errors. SystemVerilog identifier search rules Declarations in the compilation-unit scope can be referenced anywhere in the hierarchy of modules that are part of the compilation unit. the compilation- SystemVerilog defines a simple and intuitive search rule for when unit scope is referencing an identifier third in the search order 1. First search for local declarations as defined in the IEEE 1364 Verilog standard. 2. Second search for declarations in packages which have been wildcard imported into the current scope. 3. Third search for declarations in the compilation-unit scope. 4. Fourth search for declarations within the design hierarchy following IEEE 1364 Verilog search rules. The SystemVerilog search rules ensure that SystemVerilog is fully backward compatible with Verilog. Source code order NOTE Data identifiers and type definitions must be declared before being referenced. 18 SystemVerilog for Design Variables and nets in the compilation-unit scope undeclared identifiers have an implicit net type There is an important consideration when using external declarations. Verilog supports implicit type declarations where in specific contexts an undeclared identifier is assumed to be a net type typically a wire type . Verilog requires the type of identifiers to be explicitly .