tailieunhanh - The VHDL Cookbook phần 7

Khi đầu vào thiết lập lại được khẳng định, tất cả các cổng kiểm soát được trở về trạng thái ban đầu của họ, người lái xe bus dữ liệu là bị ngắt kết nối, và đăng ký máy tính được xóa. Mô hình này sau đó chờ đợi cho đến khi thiết lập lại phủ nhận trước khi tiếp tục. | 7-14 The VHDL Cookbook When the reset input is asserted all of the control ports are returned to their initial states the data bus driver is disconnected and the PC register is cleared. The model then waits until reset is negated before proceeding. Throughout the rest of the model the reset input is checked after each bus transaction. If the transaction was aborted by reset being asserted no further action is taken in fetching or executing an instruction and control falls through to the reset handling code. The instruction fetch part is simply a call to the memory read procedure. The PC register is used to provide the address the fetch flag is true and the result is returned into the current instruction register. The PC register is then incremented by one using the arithmetic procedure previously defined. The fetched instruction is next decoded into its component parts the opcode the source and destination register addresses and an immediate constant field. The op-code is then used as the selector for a case statement procedure multiply result inout bit_32 op1 op2 in integer V N Z out bit is begin if op1 0 and op2 0 or op1 0 and op2 0 -- result positive and abs op1 integer high abs op2 then -- positive overflow int_to_bits integer high result V 1 elsif op1 0 and op2 0 or op1 0 and op2 0 -- result negative and - abs op1 integer low abs op2 then -- negative overflow int_to_bits integer low result V 1 else int_to_bits op1 op2 result V 0 end if N result 31 Z bool_to_bit result X 0000_0000 end multiply procedure divide result inout bit_32 op1 op2 in integer V N Z out bit is begin if op2 0 then if op1 0 then -- positive overflow int_to_bits integer high result else int_to_bits integer low result end if V 1 else int_to_bits op1 op2 result V 0 end if N result 31 Z bool_to_bit result X 0000_0000 end divide Figure7-9 continued . 7. Sample Models The DP32 Processor 7-15 which codes the instruction execution. For the arithmetic instructions including the quick forms the .