tailieunhanh - Logic Cadence VHDL and Verilog Simulation Guide and Tutorial

sử dụng tại Đại học Cincinnati Wei Yang Tháng 1 năm 2003 (Cập nhật 04 tháng 1, H. Carter) Hướng dẫn này mô tả, thông qua một hướng dẫn, làm thế nào để thiết lập môi trường cá nhân (đường dẫn và các biến evnrionment), và mô phỏng VHDL (Verilog) mô hình sử dụng các công cụ Cadence. | Cadence VHDL Verilog Simulation Guide and Tutorial for use at the University of Cincinnati Wei Yang January 2003 Updated Jan 04 H. Carter This guide describes via a tutorial how to set up the personal environment paths and evnrionment variables and simulate VHDL or Verilog models using the Cadence tools. The tutorial describes VHDL simulation but Verilog simulation should be identical except that the model files traditionally end in .v rather than .vhd or .vhdl. The Cadence simulator can simulate either or both VHDL and Verilog models. The Cadence tools were initially acquired in 2001 and have been gaining increasing use as educators and researchers in the Electrical and Computer Engineering and Computer Science ECECS department have become familiar with them. All of the Cadence tools and documentation are located in opt CAD Cadence and can be executed only from Sun workstations served by the department servers. Since these tools are commercially licensed please do not point any URL s to them from public websites. This guide is presented in three sections 1. How to set up your environment to view the documents and run the simulator tools. You can skip this section if your environment is already set up to access the Cadence tools. 2. Executing the VHDL Verilog simulator. Two approaches can be used to simulate VHDL Verilog models 1 manually executing a series of three programs to compile elaborate and simulate the models or 2 using a GUI to perform the simulation. We describe both methods. 3. How to visualize the simulation results. How to Set Up Your Environment to Access Cadence Tools and Documents The Cadence tool set actually consists of a set of tool suites. For example there is the integrated circuit design suite which resides in the IC directory. For out purposes we are interested in the VHDL Verilog simulation tools which are in the LDV directory. For the instructions given below on adding path and enviornment information to the initialization files all .