tailieunhanh - Lumped Elements for RF and Microwave Circuits phần 3

Ngoài ra () và () cho thấy rằng tác động của lớp xen điện dung C 1 là khoảng bốn lần so với dung dưới lớp C 2. Hình (a) cho thấy một điện dẫn ba lớp. Bảng tóm tắt việc thực hiện đo chín cuộn cảm đặc trưng bằng cách sử dụng công nghệ CMOS 0,25-m. Giả sử một | 82 Lumped Elements for RF and Microwave Circuits Figure Two-level inductor fabricated using a metal 5 and metal 4 and b metal 5 and metal 3 layers. From 42 . 2001 IEEE. Reprinted with permission. Table Approximate Parasitic Capacitance Between Metal Layers and Metal and Si Substrate Metal A Metal B Cl pF m2 Metal A Metal B C2 pF m2 Metal B Substrate Ceq pF m2 M 5 M 4 40 6 14 M 5 M 3 14 9 M5 M 2 9 12 Mi designates the metal i layer. where Lt is the total inductance of the stacked inductor. From Table it is obvious that the SRF of a two-layer inductor using M5 and M2 is about twice that of the inductor using M5 and M4 layers. Also and suggest that the effect of interlayer capacitance C1 is about four times more than the bottom-layer capacitance C2. Figure a shows a three-layer inductor. Table summarizes the measured performance of nine inductors characterized using CMOS technology. Assuming a single-layer inductance of about 13 nH 45 nH divided by about in 240 mm2 square area a five-layer inductor has about 20 times more inductance compared to the conventional inductor of the same physical area using the same conductor dimensions and spacings. An alternative approach for a multilevel inductor having about four times lower Ceq has been reported 48 . Figure b shows the four-layer inductor wiring diagram with current flow. Due to slightly lower inductance value this configuration has a SRF that is approximately 34 higher than the conventional stacked inductor. Printed Inductors 83 b Figure a Conventional three-level inductor using metals 5 3 and 1 on a Si substrate. b Improved SRF four-level stacked inductor with current flow path. From 48 . 2002 IEEE. Reprinted with permission. Table Summary of Measured Performance of Stacked Inductors Fabricated in m CMOS Technology Inductor Metal Layers Number of Turns L nH Measured fres GHz L 1 240 m 2 5 4 7 45 L2 240 m 2 5 3 7 45 L3 240 m 2 5 2 7 45