tailieunhanh - The Ten Commandments of Excellent Design

Những Mười Điều Răn Chỉ trong trường hợp bạn quên, đây là Mười Điều Răn của Thiết kế xuất sắc: 1. Tất cả các kết quả đầu ra máy nhà nước luôn luôn phải được đăng ký 2. Ngươi đăng ký sử dụng, không bao giờ chốt 3. Thy đầu vào máy nhà nước, bao gồm thiết lập lại, sẽ được đồng bộ 4. | The Ten Commandments of Excellent Design VHDL Code Examples Peter Chambers Engineering Fellow VLSI Technology This short paper will give you some VHDL code examples that will help you design synchronous circuits that work first time. Those Ten Commandments Just in case you forgot here are the Ten Commandments of Excellent Design 1. All state machine outputs shall always be registered 2. Thou shalt use registers never latches 3. Thy state machine inputs including resets shall be synchronous 4. Beware fast paths lest they bite thine ankles 5. Minimize skew of thine clocks 6. Cross clock domains with the greatest of caution. Synchronize thy signals 7. Have no dead states in thy state machines 8. Have no logic with unbroken asynchronous feedback lest the fleas of myriad Test Engineers infest thee 9. All decode logic must be crafted carefully eschew asynchronicity 10. Trust not thy simulator it may beguile thee when thy design is junk How to Write Ten-Commandment Code Conforming to the Ten Commandments is not difficult. In this section you ll see how to write VHDL your author doesn t do Verilog but the translation is easy 1997 VLSI Technology 1 Ten-Commandment Code that complies with the rules. Robust design and first-silicon success are the goals The philosophy behind Ten-Commandment code is that synthesizers are not to be trusted too much. Most of the code you will see is close to the structural level some more overtly than others. Most of the code is self-explanatory. It is assumed that the reader is familiar with VHDL. Signal names are also obvious to anyone skilled in the art. Ten-Commandment Code How to Create a Flip-Flop One of the basic primitives that we need to create robust synchronous designs is the D-type flip-flop. Look at the code in Code Sample 1 -- VHDL Code for a D-Type Flip-Flop with an -- Asynchronous Clear D_Type_Flip_Flop process Reset_n Clock_In begin if Reset_n 0 then Q_Output 0 after 1 ns elsif Clock_In event and Clock_In 1 then Q_Output D_Input