tailieunhanh - MEMORY, MICROPROCESSOR, and ASIC phần 6

Do tầm quan trọng của các kỹ thuật tĩnh trong việc xác minh hành vi thời gian của bộ vi xử lý, chúng tôi sẽ hạn chế các cuộc thảo luận dưới đây để các điểm nổi bật của hỗ trợ kỹ thuật tĩnh. nhưng để giữ số lượng chu kỳ kiểm tra thấp, mức độ cần được giảm thiểu. | Timing and Signal Integrity Analysis 8-3 Because of the importance of static techniques in verifying the timing behavior of microprocessors we will restrict the discussion below to the salient points of static TA. DCC Partitioning The first step in transistor-level static TA is to partition the circuit into dc connected components DCCs also called channel-connected components. A DCC is a set ofnodes which are connected to each other through the source and drain terminals of transistors. The transistor-level representation and the DCC partitioning of a simple circuit is shown in Fig. . As seen in the diagram a DCC is the same as the gate for typical cells such as inverters NAND and NOR gates. For more complex structures such as latches a single cell corresponds to multiple DCCs. The inputs of a DCC are the primary inputs of the circuit or the gate nodes of the devices that are part of the DCC. The outputs of a FIGURE Transistor-level circuit partitioned into DCCs DCC are either primary outputs of the circuit or nodes that are connected to the gate nodes of devices in other DCCs. Since the gate current is zero and currents flow between source and drain terminals of MOS devices a MOS circuit can be partitioned at the gates of transistors into components which can then be analyzed independently. This makes the analysis computationally feasible since instead of analyzing the entire circuit we can analyze the DCCs one at a time. By partitioning a circuit into DCCs we are ignoring the current conducted by the MOS parasitic capacitances that couple the source drain and gate terminals. Since this current is typically small the error is small. As mentioned above DCC partitioning is required for transistor-level static TA. For higher levels of abstraction such as gate-level static TA the circuit has already been partitioned into gates and their inputs are known. In such cases one starts by constructing the timing graph as described in the next section. .