tailieunhanh - Examples of VHDL Descriptions p7

TYPE IS ARRAY (0 ĐẾN 5) của tương tự; giá trị mẫu cho một khoảng thời gian quý qrtrsine CONSTANT: sinevals: = (, 1,545, 2,939, 4,045, 4,755, ); bắt đầu quá trình tuần tự quá trình tạo ra sinewave BEGIN FOR i IN 0 ĐẾN 19 LOOP - đầu ra 20 mẫu cho mỗi giai đoạn | Examples of VHDL Descriptions x-e- ii I I r I Cl i r L L y 11 i J . i - L- L . when state2 if id x 7 then state state3 y 10 else Ji- jij j i state state2 r-I I -I -n I I I iri i i - 5 L - I I- Li-y 11 end if when state3 L I 1I i i i L 11 i I - ii ii I if id x 7 then state stateO y 00 L I L L L - Lil L I r I I ielsif id x 9 then - I I i I L I L I I i - I I i state state4 y 11 else state state3 y 10 end if i i I I I 11 - i i - i I I I I i i i I I 11 I i I I i . 111I i i I L when state4 jr _ L I if id x b then state state0 y 00 else state state4 y 11 end if L I II i i iiI i I i end case v i- t end if end process end archmealy Moore State Machine with explicit state encoding library ieee use entity moore2 is port clk rst in std_logic id in std_logic_vector 3 downto 0 y out std_logic_vector 1 downto 0 end moore2 architecture archmoore2 of moore2 is signal state std_logic_vector 2 downto 0 -- State assignment is such that 2 LSBs are outputs constant state0 std_logic_vector 2 downto 0 000 constant state1 std_logic_vector 2 downto 0 010 constant state2 std_logic_vector 2 downto 0 011 constant state3 std_logic_vector 2 downto 0 110 constant state4 std_logic_vector 2 downto 0 111 begin moore process clk rst begin i I L -iL _ _if rst 1 then 1 th__div state state0 - I I -_--_n r elsif clk event and clk 1 then case state is when state0 if id x 3 then k L 2 1 I - L L state state1 else state state0 http aoursewxre adveda vhdl 60 of 67 2 3 1 2002 4 1 5 0 9 Examples of VHDL Descriptions I _ I _ I_ I __ _l __end if l3L iS when statel state state2 when state2 if id x 7 then state state3 else state state2 end if when state3 _ I I I Il-n-inr _ I __ r_r _ I I I I __ _ _ if id x 7 then ---------_ I I I I . I I I I---------------_ state stateO __ I _ I II _lIl I - L L Ielsif id x 9 then Il I 111 I I I I 11I1 I i I state state4 else state state3 end if when state4 if id x b then state stateO else state state4 end if _ I I