tailieunhanh - Examples of VHDL Descriptions p6

c thể để tạo ra một lấy mẫu sinewave (lấy mẫu tại 20 khoảng thời gian chúng tôi) SỬ DỤNG , sinegen ENTITY IS PORT (sinewave: OUT tương tự), sinegen END KIẾN TRÚC hành vi của sinegen CONSTANT ts: Thời gian: = 20 chúng tôi; - mẫu khoảng sinevals | Examples of VHDL Descriptions -- WAIT FOR 2 0 us END PROCESS control_waves END block_struct Sinewave generator for testbench --entity to generate a sampled sinewave sampled at 20 us intervals USE ENTITY sinegen IS PORT sinewave OUT analogue END sinegen ARCHITECTURE behaviour OF sinegen IS CONSTANT ts TIME 2 0 us --sample interval TYPE sinevals IS ARRAY 0 TO 5 OF analogue --sample values for one quarter period CONStAnT qrtrsine sinevals BEGIN PROCESS --sequential process generates sinewave BEGIN FOR i IN 0 TO 19 LOOP --output 20 samples per period Ỵ - - IF i 0 AND i 6 THEN --first quarter period uKClViXidL _- - - sinewave qrtrsine i - -ELSIF i 6 AND i 11 THEN --second quarter period sinewave qrtrsine 10-i ELSIF i 11 AND i 16 THEN --third quarter period sinewave -qrtrsine i-10 ELSE --i IN 16 TO 19 sinewave -qrtrsine 20-i --final quater period END IF WAIT FOR ts END LOOP END PROCESS END behaviour Testbench for Digital Delay Unit USE USE ENTITY delay_bench IS PORT reset IN BIT delay IN addr10 END delay_bench ARCHITECTURE version1 OF delay_bench IS COMPONENT sinegen PORT sinewave OUT analogue END COMPONENT COMPONENT digdel2 PORT clear IN BIT offset IN addr10 sigin IN analogue sigout INOUT analogue END COMPONENT SIGNAL analogue_in analogue_out analogue BEGIN sig_gen sinegen PORT MAP analogue_in delay_unit digdel2 PORT MAP reset delay analogue_in analogue_out http aoursewxre adveda vhdl 51 of 67 2 3 1 2002 4 15 09 Examples of VHDL Descriptions END 8-bit Analogue to Digital Converter --8-bit analogue to digital converter --demonstrates use of LOOP and WAIT statements ENTITY adc8 IS GENERIC tconv TIME 10 us --conversion time _ PORT vin IN REAL RANGE TO --unipolar input digout OUT NATURAL RANGE 0 TO 255 --output J - . IN BIT busy OUT BIT --control END adc8 ARCHITECTURE behaviour OF adc8 IS BEGIN PROCESS VARIABLE digtemp NATURAL CONSTANT vlsb