tailieunhanh - Data Sheet High-Performance, Enhanced Flash Microcontrollers phần 5

Thanh toán bù trừ một chút TRISE (= 0) sẽ làm cho các pin Porte tương ứng với một đầu ra (ví dụ, đưa các nội dung của các chốt đầu ra trên pin đã chọn). Sổ đăng ký Latch dữ liệu (muộn) cũng là bộ nhớ ánh xạ. Read-chỉnh sửa-viết hoạt động từ ngày đăng ký muộn đọc và ghi giá trị sản lượng chốt cho Porte. | PIC18FXX2 REGISTER 15-3 SSPSTAT MSSP STATUS REGISTER I2C MODE R W-0 R W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D A P S R W UA BF bit 7 bit 0 bit 7 SMP Slew Rate Control bit In Master or Slave mode 1 Slew rate control disabled for Standard Speed mode 100 kHz and 1 MHz 0 Slew rate control enabled for High Speed mode 400 kHz bit 6 CKE SMBus Select bit In Master or Slave mode 1 Enable SMBus specific inputs 0 Disable SMBus specific inputs bit 5 D A Data Address bit In Master mode Reserved In Slave mode 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address bit 4 P STOP bit 1 Indicates that a STOP bit has been detected last 0 STOP bit was not detected last Note This bit is cleared on RESET and when SSPEN is cleared. bit 3 S START bit 1 Indicates that a start bit has been detected last 0 START bit was not detected last Note This bit is cleared on RESET and when SSPEN is cleared. bit 2 R W Read Write bit Information I2C mode only In Slave mode 1 Read 0 Write Note This bit holds the R W bit information following the last address match. This bit is only valid from the address match to the next START bit STOP bit or not ACK bit. In Master mode 1 Transmit is in progress 0 Transmit is not in progress Note ORing this bit with SEN RSEN PEN RCEN or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA Update Address 10-bit Slave mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated bit 0 BF Buffer Full Status bit In Transmit mode 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty In Receive mode __ 1 Data transmit in progress does not include the ACK and STOP bits SSPBUF is full 0 Data transmit complete does not include the ACK and STOP bits SSPBUF is empty Legend R Readable bit W Writable bit U Unimplemented bit read as 0 - n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2006 Microchip Technology .