tailieunhanh - Model-Based Design for Embedded Systems- P42

Model-Based Design for Embedded Systems- P42: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 376 Model-Based Design for Embedded Systems address-cells 1 size-cells 1 compatible xlnx virtex DDR2_SDRAM memory@0 device_type memory reg 0 10000000 cpus address-cells 1 size-cells 0 cpus 1 ppc405_0 cpu@0 clock-frequency ee6b280 compatible PowerPC 405 ibm ppc405 d-cache-line-size 20 d-cache-size 4000 device_type cpu i-cache-line-size 20 i-cache-size 4000 model PowerPC 405 reg 0 timebase-frequency ee6b280 plb plb@0 address-cells 1 size-cells 1 compatible xlnx ranges TriMode_MAC_GMII xps-ll-temac@81c00000 address-cells 1 size-cells 1 compatible xlnx compound ethernet@81c00000 compatible xlnx xps-ll-temac- device_type network interrupt-parent xps_intc_0 interrupts 2 2 llink-connected PIM2 local-mac-address 02 00 00 00 00 00 reg 81c00000 40 xlnx phy-type 1 xlnx temac-type 1 mpmc@0 address-cells 1 size-cells 1 compatible xlnx PIM2 sdma@84600100 compatible xlnx ll-dma- interrupt-parent xps_intc_0 interrupts 1 2 0 2 reg 84600100 80 opb opb@40000000 address-cells 1 size-cells 1 compatible xlnx ranges 40000000 40000000 10000000 opb_hwicap_0 opb-hwicap@41300000 compatible xlnx opb-hwicap- reg 41300000 10000 xlnx family virtex4 plbv46_dcr_bridge_0 plbv46-dcr-bridge@80700000 compatible xlnx plbv46-dcr-bridge- dcr-access-method mmio dcr-controller dcr-mmio-range 80700000 1000 dcr-mmio-stride 4 rs232 serial@84000000 clock-frequency 4f790d5 compatible xlnx xps-uartlite- current-speed 2580 device_type serial interrupt-parent xps_intc_0 interrupts 3 0 port-number 0 reg 84000000 10000 xlnx baudrate 2580 xlnx data-bits 8 xlnx odd-parity 0 xlnx use-parity 0 xps_bram_if_cntlr_1 xps-bram-if-cntlr@fffff000 compatible xlnx xps-bram-if-cntlr- reg fffff000 1000 xps_intc_0 interrupt-controller@81800000 interrupt-cells 2 compatible xlnx interrupt-controller reg 81800000 10000 xlnx num-intr-inputs 5 xps_socket_0 xps-socket@50000000 compatible xlnx xps-socket dcr-parent plbv46_dcr_bridge_0 .