tailieunhanh - Model-Based Design for Embedded Systems- P29

Model-Based Design for Embedded Systems- P29: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 246 Model-Based Design for Embedded Systems Ji Application Global architecture view Partitioning and mapping Inter-subsystem communication CPU I Peripherals - Intra-subsyst comm. - F S3 -iS 1 1 Task 1 Task 1 3 Task 2 Task n g Abstract intrasubsystem comm. Abstract intrasubsystem comm. Abstract inter-subsystem communication System architecture SW-SS HW-SS T . 1 . Intra-subsyst comm. HdS API Mapping comm. on HW resources Comm. archit. Virtual architecture Comm. implem. 1 SW adapt. to specific CPUs and memory Transaction accurate architecture HAL CPUs ISS Tas _ Ts Li k p p T i Task 2 Task n g HDS API Comm OS HAL API HAL CPU Peripherals . Virtual prototype . Inter-subsystem communication FIGURE MPSoC programming steps. The result of each of these four phases represents a step in the software and communication refinement process. The refinement is an incremental process. At each stage additional software component and Programming Models for MPSoC 247 architecture details are integrated with the previously generated and validated components. This results to a gradual transformation of a high level representation with abstract components and high level programming models into a concrete low level executable software code. The transformation has to be validated at each design step. The validation can be performed by formal analysis simulation or combining simulation with formal analysis 23 . In the following we will use simulation-based validation to ensure that the system behavior respects the initial specification. During the partitioning and mapping of the application on the target architecture the relationship between application and architecture is defined. This refers to the number of application tasks that can be executed in parallel the granularity of these tasks coarse grain or fine grain and the association between tasks and the processors that will execute them. The result of this step is the decomposition of the .