tailieunhanh - Model-Based Design for Embedded Systems- Part 10

Model-Based Design for Embedded Systems- P10: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 66 Model-Based Design for Embedded Systems in the application binary. Depending on the current cache state and the execution history cache misses may occur at different points in time. However formal methods are able to identify for each basic block the maximum number of cache misses that may occur during the execution 46 . The control flow graph can be annotated with this information making the longest path analyses feasible again. Depending on the actual system configuration the upper bound on the number of transactions per task execution may not be sufficiently accurate. In a formal model this could translate into an assumed burst of requests that may not occur in practice. This can be addressed with a more detailed analysis of the task control flow as is done in 1 39 which provides bounds on the minimum distances between any n requests of an activation of that task. This pattern will then repeat with each task activation. This procedure allows to conservatively derive the shared resource request bound functions fj w and fj- w that represent the transaction traffic that each task t in the system can produce within a given time window of size w. Requesting tasks that share the same processor may be executed in alternation resulting in a combined request traffic for the complete processor. This again can be expressed as an event model. For example a straightforward approach is to approximate the processor s request event model in a given time window with the aggregation of the request event models of each individual task executing on that processor. Obviously this is an overestimation as the tasks will not be executed at the same time but rather the scheduler will assign the processor exclusively. The resulting requests will be separated by the intermediate executions which can be captured in the joint shared resource request bound by a piecewise assembly from the elementary streams 39 . Response Time Analysis in the Presence of Shared Memory Accesses Memory