tailieunhanh - An Experimental Approach to CDMA and Interference Mitigation phần 8

Được giới thiệu bởi một cuộc thảo luận ngắn gọn về các vấn đề chính trong thiết kế và thực hiện các thiết bị đầu cuối viễn thông không dây (dòng chảy thiết kế, số liệu thiết kế, thăm dò không gian thiết kế, hiệu ứng số học hữu hạn, tạo mẫu nhanh chóng, vv), Chương này trình bày chi tiết việc thực hiện phần cứng FPGA của CDMA nhận | Chapter 5 INTERFERENCE MITIGATION PROCESSOR ASIC S DESIGN Is it difficult to design a CDMA receiver mitigating interference It is certainly challenging but it is no more difficult than designing a conventional DS SS receiver with some additional intelligence and processing power. The previous Chapters have shown the conventional side of the design. This Chapter on the contrary is focused on the value-added core of the MUSIC receiver the details of the ASIC design for the interference mitigation processor the so called EC-BAID. Starting with a description of the ASIC I O interface with details on the circuit pin-out along and on the timing diagram of the input output signals the chapter develops through to an overview of the serial protocol which is used for the configuration of the ASIC followed by an overall portrayal of the circuit and by detailed descriptions of each sub-block. Finally the Front to Back ASIC design flow is presented together with the resulting circuit statistics for a ym CMOS technology implementation. 1. ASIC INPUT OUTPUT INTERFACE Definition of the I O interface is one of the major drivers in the ASIC design cycle and must be considered since the very beginning of the process. The preliminary feasibility study told us that the EC-BAID circuit is characterized by a small gate complexity which implies a small ASIC core area and a pad limited layout in the selected technology HCMOS8D by STMicroelectronics see Section . For this reason in order to reduce the size of the circuit the number of I O pins was kept as low as possible and a 44 pin package was selected. The limitations caused by such choice in the receiver interface were dealt with by proper output multiplexing and by serially loading all the EC-BAID configuration parameters at startup. 186 Chapter 5 ASIC Pin-Out The pin-out of the EC-BAID ASIC is shown in Figure 5-1 while a short description of each pin function is presented in Table 1. The selected 44 pin package is the .